
`timescale 1ns/10ps

module tb_frag_clk;


//Globle Signals
parameter CLOCK_PERIOD = 10;
reg clk_sys,rst_n;
initial
begin
clk_sys = 1'b0;
rst_n = 1'b1;
#(CLOCK_PERIOD*10) rst_n = 1'b0;
#(CLOCK_PERIOD*10) rst_n = 1'b1;
end
always #(CLOCK_PERIOD/2) clk_sys <= ~clk_sys;


//DUT
wire frag_clk;

reg ad_data_vld;
reg sample_fire;
reg sample_done;

wire [31:0] cfg_sample_cnt = 32'd25;
frag_clk DUT(

    .frag_clk(frag_clk),
    .ad_data_vld(ad_data_vld),

    .sample_fire(sample_fire),
    .sample_done(sample_done),

    .cfg_sample_cnt(cfg_sample_cnt),

    .clk_sys(clk_sys),
    .rst_n(rst_n)

    );



//Test State Machine
reg [1:0] sta_test;
localparam IDLE  = 2'h0,
           START = 2'h1,
           VILAD = 2'h2,
           DONE  = 2'h3;

reg [31:0] cnt_wait;
always @ (posedge clk_sys or negedge rst_n)
begin
if (rst_n == 1'b0)
    sta_test <= IDLE;
else
    begin
    case (sta_test)
        IDLE:
            if (cnt_wait >= 32'h20)
                sta_test <= START;
        START:
            if (cnt_wait == 32'h4)
                sta_test <= VILAD;
        VILAD:
            if (cnt_wait >= cfg_sample_cnt)
                sta_test <= DONE;
        DONE:
            sta_test <= IDLE;
        default:
            sta_test <= IDLE;
    endcase
    end
end


//Test Control
always @(posedge clk_sys or negedge rst_n)
begin
if (rst_n == 1'b0)
    cnt_wait <= 32'h0;
else
    begin
    case (sta_test)
        IDLE:
            if (cnt_wait >= 32'h20)
                cnt_wait <= 32'h0;
            else
                cnt_wait <= cnt_wait + 32'h1;
        START:
            if (cnt_wait >= 32'h4)
                cnt_wait <= 32'h0;
            else
                cnt_wait <= cnt_wait + 32'h1;
        VILAD:
            cnt_wait <= cnt_wait + 32'h1;
        DONE:
            cnt_wait <= 32'h0;
    endcase
    end
end

//reg ad_data_vld;
always @ (posedge clk_sys)
    ad_data_vld <= (sta_test == VILAD && cnt_wait >= 32'h1 && cnt_wait <= cfg_sample_cnt) ? 1'b1 : 1'b0;
//reg sample_fire;
always @ (posedge clk_sys)
    sample_fire <= (sta_test == START && cnt_wait == 32'h0) ? 1'b1 : 1'b0;
//reg sample_done;
always @ (posedge clk_sys)
    sample_done <= (sta_test == DONE) ? 1'b1 : 1'b0;

reg [31:0] cnt_flag;
always @ (posedge clk_sys)
    cnt_flag <= (sta_test == VILAD) ? cnt_wait : 32'h0;


//Test Result
/*
always @ (posedge clk_sys)
begin
if (uart_rx_vld)
    begin
    if (uart_rx_data == data_tested)
        $display("Uart Data Right!\n");
    else
        $display("Uart Data Wrong!\n");
    end
end
always @ (posedge clk_sys)
begin
case (uart_rx_err)
    2'h0: if (uart_rx_vld) $display("Parity Check Pass!\n");
    2'h1: if (uart_rx_vld) $display("Parity Check Fail!\n");
    2'h2: $display("Start Bit Error!\n");
    2'h3: $display("Stop Bit Error!\n");
endcase
end
*/

//Debussy Simulation Wave File
initial
begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars;
end


endmodule
